An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic

We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores results in a network that is fast and highly hardware-compact. The proposed architecture for prefix counting N 1 bits features a total delay of (4 logN +pN 2) Td, where Td is the delay for charging or discharging a row of two prefix sum units of eight shift switches. Simulation results reveal that Td does not exceed 1ns under 0.8-micron CMOS technology. Our design is faster than any design known to us for N 210. Yet another important and novel feature of the proposed architecture is that it requires very simple controls, partially driven by semaphores, reducing significantly the hardware complexity and fully utilizing the inherent speed of the process.